A semiconductor integrated circuit chip is typically fabricated with a back-end-of-line (BEOL) interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias. The BEOL interconnect structure serves to connect various integrated circuit components and devices that are fabricated as part of a front-end-of-line (FEOL) layer of the semiconductor integrated circuit chip. Current state of the art BEOL process technologies typically implement copper to form BEOL interconnect structures, as the low resistivity of copper material significantly reduces resistance in the BEOL interconnect structure, resulting in improved conduction and higher performance. Conventional process flows for fabricating copper interconnect structures utilize a chemical-mechanical planarizing (CMP) process to remove overburden copper material and overburden liner material from an upper surface of an interlayer dielectric (ILD) layer in which copper interconnect structures are formed, as well as planarize the upper surface of the ILD layer. The use of CMP to remove overburden liner material can result in poor quality copper interconnects for various reasons.
For example, due to a non-uniform surface topography, a certain amount of over polish of the ILD layer is required to ensure that all of the overburden metallic liner material is removed from the surface of the ILD layer so that electrical shorts are avoided in the BEOL interconnect network. The over polishing of the ILD layer also results in removing of an upper portion of the copper metallization formed in the ILD layer, which typically comprises high quality copper material (large metallic grains), while leaving lower quality copper material (smaller metallic grains) in the lower portion of the copper metallization. As such, the resulting copper metallization has increased resistance. Furthermore, the over polishing of the surface of the ILD layer results in copper “dishing” of the upper surface of the copper metallization due to the fact that copper polishing rate is typically higher than the polishing rate of the metallic liner material and the dielectric material of the ILD layer. As such, the use of CMP in BEOL process flows can lead to increased electrical resistivity and degraded interconnect reliability.